From the first invention of integrated circuits in 1960, the number of devices on a chip has grown at an explosively increasing rate. The technologies of the semiconductor industry have been researched continuously for almost four decades. The progress of the semiconductor integrated circuits has entered the ULSI (ultra large scale integration) level or even higher a level. The capacity of a single semiconductor chip increases from several thousand devices to hundreds of million devices, or even billions of devices. The integrated circuit devices like transistors, capacitors, and connections must be greatly narrowed simultaneously. The increasing packing density of the integrated circuits generates numerous challenges to the semiconductor manufacturing process. Every device needs to be formed within a smaller size without damaging the characteristics and the operations. The demands on high packing density, low heat generating, and low power consumption devices with good reliability and long operation life must be maintained without any degradation in their functions. These achievements are expected to be reached with the five key aspects of the semiconductor manufacturing, including the photography, the etching, the deposition, the ion implantation, and the thermal processing technologies. The continuous increase in the packing density of the integration circuits must be accompanied with a smaller feature size. With the present semiconductor manufacturing technology, the processes with generally a quarter micrometer in size is widely utilized. For making the next generation devices, the technologies focusing mainly on one-tenth micrometer and even nanometer feature sizes are highly required.
Transistors, or more particularly the metal oxide semiconductor field effect transistors (MOSFET), are the most important and frequently employed devices. The MOSFET is widely employed in the integrated circuits with its high performance. However, with the continuous narrowing of device size, the sub-micron scale MOS transistors have to face many risky challenges. As the MOS transistors become narrower and thinner accompanying shorter channels, problems like junction punchthrough, leakage, and contact resistance cause the reduction in the yield and compromise the reliability of the semiconductor manufacturing processes.
For developing future MOS devices with a sub-micrometer or even smaller feature size, the ultra shallow junctions are required to suppress the short channel effects encountered with the down scaled sizes. On the other hand, new challenges arise with a narrowed size. The preparation of an extremely shallow source/drain junction is much harder. The conventional ion implantation process is unable to form a shallow junction with high dopant concentration. In the work proposed by K. Takeuchi et al. ("High performance sub-tenth micron CMOS using advanced boron doping and WSi.sub.2 dual gate process", appearing in 1995 Symposium on VLSI Technology Digest of Technical Papers), the problem is addressed. The ion implantation has difficulty in forming shallow and high concentration source/drain. The defect-induced anomalous diffusion of boron in the channel region becomes a problem. Local boron depletion near the source/drain junctions will directly enhance short channel effects. A CMOS fabrication method is also disclosed in this work.
In addition, a device degradation problem is found to come from the boron penetration into the thin gate oxide with the formation of a doped polysilicon gate. S. L. Wu (the inventor of the present invention), C. L. Lee, and T. F. Lai consider the problem in their work "Suppression of Boron Penetration into an Ultra-Thin Gate Oxide (.ltoreq.7 nm) by Using a Stacked-Amorphous-Silicon (SAS) Film" (IEDM 93-329, 1993 IEEE). The p+ polysilicon has been widely used as the gate material in pMOSFET, to avoid short-channel effects. The BF.sub.2 -implant is typically used in forming both the gate and the junction. However, the F-incorporation will enhance the boron penetration through the thin gate oxide into the silicon substrate. The penetration also results in a large threshold voltage shift. A SAS gate structure is proposed to suppress the F-incorporation-induced boron penetration effect in their work.